1. Field of the Invention
The invention generally relates to memory devices, and more particularly to reducing current consumption of memory devices.
2. Description of the Related Art
Users of electronic devices often desire large amounts of memory in a small package. Where the electronic devices are portable (e.g., battery powered), users may also desire electronic devices which do not consume as much power and therefore have a longer battery life. Thus, manufacturers of electronic devices typically desire small, high density memory devices with low power consumption. Of particular importance is the amount of current consumed when the memory devices are in a standby mode (i.e., standby current), which typically has a specified maximum value. To meet the demand for small, high density memory devices, memory manufacturers have created dynamic random access memory (DRAM) devices with the smallest available features (e.g., transistors and control lines) and with densely packed memory cells. Examples of DRAM devices include single data rate (SDR) and double data rate (DDR) DRAM devices, pseudo static random access memory (PSRAM) devices, and the like, all collectively referred to herein as DRAM devices.
However, as the size of features in a memory chip shrinks and as the memory density of a memory chip increases, small, uncontrollable errors in the manufacturing process may cause defects at a high cost to the manufacturer. An example of a possible defect is a short (e.g., an unintended electrical connection) between a wordline and a bitline used to access a memory cell. In some bitline structures, these shorts may result in increased standby current due to voltage differences created between the wordline and bitline when the bitline is maintained at a precharge voltage level.
For example, FIG. 1 illustrates an exemplary DRAM bitline structure 100 in which equalization circuitry 110 maintains complementary bitline pairs 102 at a precharge voltage level (VBLEQ) when wordlines 104 are not activated to access corresponding memory cells 101. In the “folded” bit line structure shown, left and right side bit line pairs (102L and 102R) share a common set of bit line sense amplifier (BLSA) 120. I/O gate 130 drives the output of the sense amplifier out of the array (e.g., to a secondary sense amplifier) in conjunction with a column select line (CSL) signal.
Switches (or switches) 140L and 140R are provided to select whether the left or right side bit line pairs are coupled to the BLSA 120, to access memory cells 101 in the left or ride side of the array, respectively. In other words, when accessing memory cells 101R on the right side, switch 140R may be turned on to couple complementary bit line pair 102R to BLSA 120, while switch 140L may be turned off to isolate complementary bit line pair 102L to BLSA 120. Similarly, when accessing memory cells 101R on the left side, multiplexor (or switch) 140L may be turned on while switch 140R may be turned off.
For some embodiments, separate equalization circuits 110 (provided outside the switches 140) may be provided for each complementary bit line pair 102L and 102R. However, a single equalization circuitry 110 located between the switches 140, as shown, may be shared between both complementary bit line pairs and provide a more compact design.
FIG. 2 illustrates an exemplary precharge and equalization circuit 110, controlled by an equalization signal (EQ). As illustrated, the circuit 110 may include a separate equalization circuit (MEQ) 112 which illustratively includes an N-type transistor for coupling both bit lines of a complimentary bit lines 102 together in response to the EQ signal, thereby causing the bit lines to reach a common voltage level (i.e., equalize). A separate precharge circuit (MBLEQ) 114 illustratively includes a pair of N-type transistors to apply a precharge voltage signal (VLBEQ) to both bit lines in response to the EQ signal.
The timing diagram shown in FIG. 3 illustrates how the equalization circuit 110 operates to equalize and precharge complementary bit line pairs before and after a row access. As illustrated, prior to the row access (time T5), both switches are turned on (MUX_L and MUX_R=HI) and EQ is asserted, thereby allowing bit line pairs on both sides to be equalized and precharged (to VBLEQ). The access begins at T1, for example, with a Row_Active signal being asserted, which causes the switch 140 for the side not being accessed to be turned off (illustratively, a left side access is performed) and the EQ signal to be de-asserted, thereby decoupling the bit lines. At time T2, the selected word line (e.g., one the left side) is activated and sensing of corresponding memory cells occurs in period T3.
In period T4, the selected wordline is de-activated, the switch 140 for the non-selected side is again turned on, and the EQ signal is again asserted. To ensure none of the corresponding memory cells are coupled to the bit lines, a zero voltage or negative voltage is typically applied to de-activated wordlines, resulting in a voltage difference between the wordlines and bitlines. Asserting the EQ signal and turning on both switches 140 ensures the bit lines are equalized and maintained (in period T5) at the VBLEQ by equalization circuit 110 until the next access.
Unfortunately, this approach results in increased current draw in the event a defect causes a short 402 between a (defective) wordline 104D and a bitline 102, as shown in FIG. 4. Even thought the defective wordline would likely be replaced by redundancy, due to the difference in voltage between the defective wordline 104D (maintained at 0V or less) and the bitline 102 (maintained at VBLEQ), current (ISHORT) may flow from the equalization circuit 110 to the defective wordline across the short. Compounding the problem, in case the defective wordline 104D is maintained at a negative voltage (below 0V), a charge pump, which has inherent inefficiencies, is typically utilized. For example, assuming 50% efficiency, the charge pump has to consume twice as much current to generate ISHORT.
As previously described, standby current consumption is particularly important for low powered memory devices. In some cases, increased current consumption due to bitline shorts may result in a memory device exceeding the specified minimum standby current, thereby resulting in decreased production yield. Accordingly, what is needed are methods and apparatuses for reducing standby current consumption of a memory device due to bitline shorts.